sources
sources
/app/public/buildbox/8a28c38c-73b9-4cfc-b785-d9b7213ecd6b/main.go
func scalarComputation(a, b, c []float32) {
for i := 0; i < len(a); i += 1 {
c[i] = (a[i]*a[i] + b[i]*b[i]) * -1.0
}
}
AST
AST buildssa-enter
buildssa-body
. DCL l(4)
. . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. AS l(4) colas(true) tc(1)
. . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . LITERAL-0 l(4) tc(1) int
. FOR l(4) tc(1)
. . LT-init
. . . AS l(4) tc(1)
. . . . NAME-main..autotmp_4 l(4) x(0) class(PAUTO) esc(N) tc(1) assigned used int
. . . . LEN l(4) tc(1) int
. . . . . NAME-main.a g(1) l(3) x(0) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . LT l(4) tc(1) hascall bool
. . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . NAME-main..autotmp_4 l(4) x(0) class(PAUTO) esc(N) tc(1) assigned used int
. . BLOCK l(4)
. . BLOCK-list
. . . AS l(4) tc(1) int
. . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . ADD l(4) tc(1) int
. . . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . . LITERAL-1 l(4) tc(1) int
. FOR-body
. . VARKILL l(4) tc(1)
. . . NAME-main..autotmp_4 l(4) x(0) class(PAUTO) esc(N) tc(1) assigned used int
. . AS l(5) tc(1) hascall
. . . INDEX l(5) tc(1) hascall float32
. . . . NAME-main.c g(3) l(3) x(48) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . MUL l(5) tc(1) hascall float32
. . . . ADD l(5) tc(1) hascall float32
. . . . . MUL l(5) tc(1) hascall float32
. . . . . . INDEX l(5) tc(1) hascall float32
. . . . . . . NAME-main.a g(1) l(3) x(0) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . . . . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . . . INDEX l(5) tc(1) hascall float32
. . . . . . . NAME-main.a g(1) l(3) x(0) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . . . . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . . MUL l(5) tc(1) hascall float32
. . . . . . INDEX l(5) tc(1) hascall float32
. . . . . . . NAME-main.b g(2) l(3) x(24) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . . . . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . . . INDEX l(5) tc(1) hascall float32
. . . . . . . NAME-main.b g(2) l(3) x(24) class(PPARAM) esc(no) tc(1) used SLICE-@0
. . . . . . . NAME-main.i g(4) l(4) x(0) class(PAUTO) esc(no) tc(1) assigned used int
. . . . LITERAL--1 l(5) tc(1) float32
. VARKILL l(4) tc(1)
. . NAME-main..autotmp_4 l(4) x(0) class(PAUTO) esc(N) tc(1) assigned used int
buildssa-exit
start
start b1 :- v1 (?) = InitMem <mem>v2 (?) = SP <uintptr>v3 (?) = SB <uintptr>v4 (?) = LocalAddr <*[]float32> {a} v2 v1 v5 (?) = LocalAddr <*[]float32> {b} v2 v1 v6 (?) = LocalAddr <*[]float32> {c} v2 v1 v7 (3 ) = Arg <[]float32> {a} (a[[]float32])v8 (3 ) = Arg <[]float32> {b} (b[[]float32])v9 (3 ) = Arg <[]float32> {c} (c[[]float32])v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]Plain → b2 (4) b2 : ← b1 b4 - v11 (4 ) = Phi <[]float32> v7 v25 (a[[]float32])v13 (4 ) = Phi <int> v10 v72 (i[int])v74 (5 ) = Phi <[]float32> v9 v60 (c[[]float32])v75 (5 ) = Phi <[]float32> v8 v46 (b[[]float32])v76 (5 ) = Phi <mem> v1 v69 v12 (4) = SliceLen <int> v11 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v15 (5 ) = Copy <[]float32> v11 (a[[]float32])v16 (5 ) = Copy <int> v13 (i[int])v17 (5) = SliceLen <int> v15 v18 (5) = IsInBounds <bool> v16 v17 If v18 → b6 b7 (likely) (5) b4 : ← b14 - v70 (4 ) = Copy <int> v61 (i[int])v72 (4) = Add64 <int> v70 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v15 v22 (5) = PtrIndex <*float32> v21 v16 v23 (5 ) = Copy <mem> v76 v24 (5) = Load <float32> v22 v23 v25 (5 ) = Copy <[]float32> v15 (a[[]float32])v26 (5 ) = Copy <int> v16 (i[int])v27 (5) = SliceLen <int> v25 v28 (5) = IsInBounds <bool> v26 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v19 (5 ) = Copy <mem> v76 v20 (5) = PanicBounds <mem> [0] v16 v17 v19 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v25 v32 (5) = PtrIndex <*float32> v31 v26 v33 (5 ) = Copy <mem> v23 v34 (5) = Load <float32> v32 v33 v35 (5) = Mul32F <float32> v24 v34 v36 (5 ) = Copy <[]float32> v75 (b[[]float32])v37 (5 ) = Copy <int> v26 (i[int])v38 (5) = SliceLen <int> v36 v39 (5) = IsInBounds <bool> v37 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v29 (5 ) = Copy <mem> v23 v30 (5) = PanicBounds <mem> [0] v26 v27 v29 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v36 v43 (5) = PtrIndex <*float32> v42 v37 v44 (5 ) = Copy <mem> v33 v45 (5) = Load <float32> v43 v44 v46 (5 ) = Copy <[]float32> v36 (b[[]float32])v47 (5 ) = Copy <int> v37 (i[int])v48 (5) = SliceLen <int> v46 v49 (5) = IsInBounds <bool> v47 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v40 (5 ) = Copy <mem> v33 v41 (5) = PanicBounds <mem> [0] v37 v38 v40 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v46 v53 (5) = PtrIndex <*float32> v52 v47 v54 (5 ) = Copy <mem> v44 v55 (5) = Load <float32> v53 v54 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v60 (5 ) = Copy <[]float32> v74 (c[[]float32])v61 (5 ) = Copy <int> v47 (i[int])v62 (5) = SliceLen <int> v60 v63 (5) = IsInBounds <bool> v61 v62 If v63 → b14 b15 (likely) (5) b13 : ← b10 - v50 (5 ) = Copy <mem> v44 v51 (5) = PanicBounds <mem> [0] v47 v48 v50 Exit v51 (5) b14 : ← b12 - v66 (5) = SlicePtr <*float32> v60 v67 (5) = PtrIndex <*float32> v66 v61 v68 (5 ) = Copy <mem> v54 v69 (5) = Store <mem> {float32} v67 v59 v68 Plain → b4 (5) b15 : ← b12 - v64 (5 ) = Copy <mem> v54 v65 (5) = PanicBounds <mem> [0] v61 v62 v64 Exit v65 (5) name a[[]float32]: v7 v11 v15 v25 name b[[]float32]: v8 v36 v46 v75 name c[[]float32]: v9 v60 v74 name i[int]: v10 v13 v16 v26 v37 v47 v61 v70 v72
number lines + early phielim
number lines [45609 ns] early phielim [66130 ns] b1 :- v1 (?) = InitMem <mem>v2 (?) = SP <uintptr>v3 (?) = SB <uintptr>v4 (?) = LocalAddr <*[]float32> {a} v2 v1 v5 (?) = LocalAddr <*[]float32> {b} v2 v1 v6 (?) = LocalAddr <*[]float32> {c} v2 v1 v7 (3 ) = Arg <[]float32> {a} (a[[]float32])v8 (3 ) = Arg <[]float32> {b} (b[[]float32])v9 (3 ) = Arg <[]float32> {c} (c[[]float32])v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v11 (4 ) = Copy <[]float32> v7 (a[[]float32])v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 v74 (5 ) = Copy <[]float32> v9 (c[[]float32])v75 (5 ) = Copy <[]float32> v8 (b[[]float32])If v14 → b3 b5 (likely) (4) b3 : ← b2 - v15 (5 ) = Copy <[]float32> v7 (a[[]float32])v16 (5 ) = Copy <int> v13 (i[int])v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b14 - v70 (4 ) = Copy <int> v13 (i[int])v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v23 (5 ) = Copy <mem> v76 v24 (5) = Load <float32> v22 v76 v25 (5 ) = Copy <[]float32> v7 (a[[]float32])v26 (5 ) = Copy <int> v13 (i[int])v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v19 (5 ) = Copy <mem> v76 v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v33 (5 ) = Copy <mem> v76 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v36 (5 ) = Copy <[]float32> v8 (b[[]float32])v37 (5 ) = Copy <int> v13 (i[int])v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v29 (5 ) = Copy <mem> v76 v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v44 (5 ) = Copy <mem> v76 v45 (5) = Load <float32> v43 v76 v46 (5 ) = Copy <[]float32> v8 (b[[]float32])v47 (5 ) = Copy <int> v13 (i[int])v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v40 (5 ) = Copy <mem> v76 v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v54 (5 ) = Copy <mem> v76 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v60 (5 ) = Copy <[]float32> v9 (c[[]float32])v61 (5 ) = Copy <int> v13 (i[int])v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b14 b15 (likely) (5) b13 : ← b10 - v50 (5 ) = Copy <mem> v76 v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b14 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v68 (5 ) = Copy <mem> v76 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b4 (5) b15 : ← b12 - v64 (5 ) = Copy <mem> v76 v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 v11 v15 v25 name b[[]float32]: v8 v36 v46 v75 name c[[]float32]: v9 v60 v74 name i[int]: v10 v13 v16 v26 v37 v47 v61 v70 v72
early copyelim
early copyelim [2616 ns] b1 :- v1 (?) = InitMem <mem>v2 (?) = SP <uintptr>v3 (?) = SB <uintptr>v4 (?) = LocalAddr <*[]float32> {a} v2 v1 v5 (?) = LocalAddr <*[]float32> {b} v2 v1 v6 (?) = LocalAddr <*[]float32> {c} v2 v1 v7 (3 ) = Arg <[]float32> {a} (a[[]float32])v8 (3 ) = Arg <[]float32> {b} (b[[]float32])v9 (3 ) = Arg <[]float32> {c} (c[[]float32])v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v11 (4 ) = Copy <[]float32> v7 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 v74 (5 ) = Copy <[]float32> v9 v75 (5 ) = Copy <[]float32> v8 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v15 (5 ) = Copy <[]float32> v7 v16 (5 ) = Copy <int> v13 v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b14 - v70 (4 ) = Copy <int> v13 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v23 (5 ) = Copy <mem> v76 v24 (5) = Load <float32> v22 v76 v25 (5 ) = Copy <[]float32> v7 v26 (5 ) = Copy <int> v13 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v19 (5 ) = Copy <mem> v76 v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v33 (5 ) = Copy <mem> v76 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v36 (5 ) = Copy <[]float32> v8 v37 (5 ) = Copy <int> v13 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v29 (5 ) = Copy <mem> v76 v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v44 (5 ) = Copy <mem> v76 v45 (5) = Load <float32> v43 v76 v46 (5 ) = Copy <[]float32> v8 v47 (5 ) = Copy <int> v13 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v40 (5 ) = Copy <mem> v76 v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v54 (5 ) = Copy <mem> v76 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v60 (5 ) = Copy <[]float32> v9 v61 (5 ) = Copy <int> v13 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b14 b15 (likely) (5) b13 : ← b10 - v50 (5 ) = Copy <mem> v76 v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b14 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v68 (5 ) = Copy <mem> v76 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b4 (5) b15 : ← b12 - v64 (5 ) = Copy <mem> v76 v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 v7 v7 v7 name b[[]float32]: v8 v8 v8 v8 name c[[]float32]: v9 v9 v9 name i[int]: v10 v13 v13 v13 v13 v13 v13 v13 v72
early deadcode
early deadcode [29441 ns] b1 :- v1 (?) = InitMem <mem>v7 (3 ) = Arg <[]float32> {a} (a[[]float32])v8 (3 ) = Arg <[]float32> {b} (b[[]float32])v9 (3 ) = Arg <[]float32> {c} (c[[]float32])v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b14 - v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v24 (5) = Load <float32> v22 v76 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v45 (5) = Load <float32> v43 v76 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b14 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b14 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b4 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
short circuit
short circuit [3597 ns] b1 :- v1 (?) = InitMem <mem>v7 (3 ) = Arg <[]float32> {a} (a[[]float32])v8 (3 ) = Arg <[]float32> {b} (b[[]float32])v9 (3 ) = Arg <[]float32> {c} (c[[]float32])v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v24 (5) = Load <float32> v22 v76 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v45 (5) = Load <float32> v43 v76 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
decompose args
decompose args [46202 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v24 (5) = Load <float32> v22 v76 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v45 (5) = Load <float32> v43 v76 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
decompose user + pre-opt deadcode
decompose user [1323 ns] pre-opt deadcode [8912 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = PtrIndex <*float32> v66 v13 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v22 (5) = PtrIndex <*float32> v21 v13 v24 (5) = Load <float32> v22 v76 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = PtrIndex <*float32> v31 v13 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = PtrIndex <*float32> v42 v13 v45 (5) = Load <float32> v43 v76 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = PtrIndex <*float32> v52 v13 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Mul32F <float32> v57 v58 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
opt
opt [35073 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v72 (+4 ) = Add64 <int> v13 v71 (i[int])v29 (5) = Const64 <int> [4]v70 (5) = Const64 <uint64> [2]v44 (5) = Lsh64x64 <int> [false] v13 v70 v67 (5) = AddPtr <*float32> v66 v44 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 v36 (5) = Const64 <int> [4]v16 (5) = Const64 <uint64> [2]v37 (5) = Lsh64x64 <int> [false] v13 v16 v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 v19 (5) = Const64 <int> [4]v15 (5) = Const64 <uint64> [2]v33 (5) = Lsh64x64 <int> [false] v13 v15 v32 (5) = AddPtr <*float32> v31 v33 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 v25 (5) = Const64 <int> [4]v75 (5) = Const64 <uint64> [2]v26 (5) = Lsh64x64 <int> [false] v13 v75 v43 (5) = AddPtr <*float32> v42 v26 v45 (5) = Load <float32> v43 v76 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 v73 (5) = Const64 <int> [4]v74 (5) = Const64 <uint64> [2]v23 (5) = Lsh64x64 <int> [false] v13 v74 v53 (5) = AddPtr <*float32> v52 v23 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
zero arg cse
zero arg cse [15288 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v58 (?) = Const32F <float32> [-1]v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v29 (5) = Const64 <int> [4]v70 (5) = Const64 <uint64> [2]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v72 (+4 ) = Add64 <int> v13 v71 (i[int])v44 (5) = Lsh64x64 <int> [false] v13 v70 v67 (5) = AddPtr <*float32> v66 v44 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 v37 (5) = Lsh64x64 <int> [false] v13 v70 v36 (5) = Const64 <int> [4]v16 (5) = Const64 <uint64> [2]v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 v33 (5) = Lsh64x64 <int> [false] v13 v70 v19 (5) = Const64 <int> [4]v15 (5) = Const64 <uint64> [2]v32 (5) = AddPtr <*float32> v31 v33 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 v26 (5) = Lsh64x64 <int> [false] v13 v70 v25 (5) = Const64 <int> [4]v75 (5) = Const64 <uint64> [2]v43 (5) = AddPtr <*float32> v42 v26 v45 (5) = Load <float32> v43 v76 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 v23 (5) = Lsh64x64 <int> [false] v13 v70 v73 (5) = Const64 <int> [4]v74 (5) = Const64 <uint64> [2]v53 (5) = AddPtr <*float32> v52 v23 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
opt deadcode
opt deadcode [11203 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v70 (5) = Const64 <uint64> [2]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (+5 ) = SliceLen <int> v7 v18 (5) = IsInBounds <bool> v13 v17 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v72 (+4 ) = Add64 <int> v13 v71 (i[int])v44 (5) = Lsh64x64 <int> [false] v13 v70 v67 (5) = AddPtr <*float32> v66 v44 v69 (5) = Store <mem> {float32} v67 v59 v76 Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v27 v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 If v28 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v17 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 v33 (5) = Lsh64x64 <int> [false] v13 v70 v32 (5) = AddPtr <*float32> v31 v33 v34 (5) = Load <float32> v32 v76 v35 (5) = Mul32F <float32> v24 v34 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v27 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v48 v26 (5) = Lsh64x64 <int> [false] v13 v70 v43 (5) = AddPtr <*float32> v42 v26 v45 (5) = Load <float32> v43 v76 If v49 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 v23 (5) = Lsh64x64 <int> [false] v13 v70 v53 (5) = AddPtr <*float32> v52 v23 v55 (5) = Load <float32> v53 v76 v56 (5) = Mul32F <float32> v45 v55 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v48 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
generic cse
generic cse [50033 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v70 (5) = Const64 <uint64> [2]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v17 (5 ) = SliceLen <int> v7 v18 (+5 ) = IsInBounds <bool> v13 v12 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = AddPtr <*float32> v66 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])v44 (5) = Lsh64x64 <int> [false] v13 v70 Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v27 (5) = SliceLen <int> v7 v28 (5) = IsInBounds <bool> v13 v12 v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 If v18 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v20 (5) b8 : ← b6 - v31 (5) = SlicePtr <*float32> v7 v32 (5) = AddPtr <*float32> v21 v37 v34 (5) = Load <float32> v22 v76 v35 (5) = Mul32F <float32> v24 v24 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 v33 (5) = Lsh64x64 <int> [false] v13 v70 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = AddPtr <*float32> v42 v37 v45 (5) = Load <float32> v43 v76 v48 (5) = SliceLen <int> v8 v49 (5) = IsInBounds <bool> v13 v38 v26 (5) = Lsh64x64 <int> [false] v13 v70 If v39 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v52 (5) = SlicePtr <*float32> v8 v53 (5) = AddPtr <*float32> v42 v37 v55 (5) = Load <float32> v43 v76 v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 v23 (5) = Lsh64x64 <int> [false] v13 v70 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
phiopt + gcse deadcode
phiopt [762 ns] gcse deadcode [11131 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v70 (5) = Const64 <uint64> [2]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v18 (+5 ) = IsInBounds <bool> v13 v12 If v18 → b6 b7 (likely) (5) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = AddPtr <*float32> v66 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 If v18 → b8 b9 (likely) (5) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v20 (5) b8 : ← b6 - v35 (5) = Mul32F <float32> v24 v24 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = AddPtr <*float32> v42 v37 v45 (5) = Load <float32> v43 v76 If v39 → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
nilcheckelim + prove
nilcheckelim [11247 ns] prove [62581 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a}v68 (3 ) = Arg <int> {a} [8]v50 (3 ) = Arg <int> {a} [16]v61 (3 ) = Arg <*float32> {b}v60 (3 ) = Arg <int> {b} [8]v54 (3 ) = Arg <int> {b} [16]v40 (3 ) = Arg <*float32> {c}v47 (3 ) = Arg <int> {c} [8]v46 (3 ) = Arg <int> {c} [16]v70 (5) = Const64 <uint64> [2]v23 (?) = Const64 <int64> [0]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 (a[[]float32])v8 (3 ) = SliceMake <[]float32> v61 v60 v54 (b[[]float32])v9 (3 ) = SliceMake <[]float32> v40 v47 v46 (c[[]float32])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v12 (+4 ) = SliceLen <int> v7 v14 (4) = Less64 <bool> v13 v12 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v18 (+5 ) = IsInBounds <bool> v13 v12 First → b6 b7 (likely) (+5 ) b4 : ← b12 - v66 (5) = SlicePtr <*float32> v9 v67 (5) = AddPtr <*float32> v66 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v21 (5) = SlicePtr <*float32> v7 v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v21 v37 v24 (5) = Load <float32> v22 v76 First → b8 b9 (likely) (+5 ) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v20 (5) b8 : ← b6 - v35 (5) = Mul32F <float32> v24 v24 v38 (5) = SliceLen <int> v8 v39 (5) = IsInBounds <bool> v13 v38 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v12 v76 Exit v30 (5) b10 : ← b8 - v42 (5) = SlicePtr <*float32> v8 v43 (5) = AddPtr <*float32> v42 v37 v45 (5) = Load <float32> v43 v76 First → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v41 (5) b12 : ← b10 - v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v62 (5) = SliceLen <int> v9 v63 (5) = IsInBounds <bool> v13 v62 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v38 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v62 v76 Exit v65 (5) name a[[]float32]: v7 name b[[]float32]: v8 name c[[]float32]: v9 name i[int]: v10 v13 v72
early fuse + decompose builtin
early fuse [1380 ns] decompose builtin [46619 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v50 (3 ) = Arg <int> {a} [16] (a+16[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v54 (3 ) = Arg <int> {b} [16] (b+16[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])v46 (3 ) = Arg <int> {c} [16] (c+16[int])v70 (5) = Const64 <uint64> [2]v23 (?) = Const64 <int64> [0]v7 (3 ) = SliceMake <[]float32> v64 v68 v50 v8 (3 ) = SliceMake <[]float32> v61 v60 v54 v9 (3 ) = SliceMake <[]float32> v40 v47 v46 Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v14 (+4 ) = Less64 <bool> v13 v68 If v14 → b3 b5 (likely) (4) b3 : ← b2 - v18 (+5 ) = IsInBounds <bool> v13 v68 First → b6 b7 (likely) (+5 ) b4 : ← b12 - v67 (5) = AddPtr <*float32> v40 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v64 v37 v24 (5) = Load <float32> v22 v76 First → b8 b9 (likely) (+5 ) b7 : ← b3 - v20 (5) = PanicBounds <mem> [0] v13 v68 v76 Exit v20 (5) b8 : ← b6 - v35 (5) = Mul32F <float32> v24 v24 v39 (5) = IsInBounds <bool> v13 v60 If v39 → b10 b11 (likely) (5) b9 : ← b6 - v30 (5) = PanicBounds <mem> [0] v13 v68 v76 Exit v30 (5) b10 : ← b8 - v43 (5) = AddPtr <*float32> v61 v37 v45 (5) = Load <float32> v43 v76 First → b12 b13 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b10 - v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v63 (5) = IsInBounds <bool> v13 v47 If v63 → b4 b15 (likely) (5) b13 : ← b10 - v51 (5) = PanicBounds <mem> [0] v13 v60 v76 Exit v51 (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name a+16[int]: v50 name b[*float32]: v61 name b+8[int]: v60 name b+16[int]: v54 name c[*float32]: v40 name c+8[int]: v47 name c+16[int]: v46 name i[int]: v10 v13 v72
softfloat + late opt + dead auto elim + generic deadcode
softfloat [587 ns] late opt [9338 ns] dead auto elim [3214 ns] generic deadcode [11963 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])v70 (5) = Const64 <uint64> [2]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v14 (+4 ) = Less64 <bool> v13 v68 If v14 → b3 b5 (likely) (4) b4 : ← b12 - v67 (5) = AddPtr <*float32> v40 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b6 : ← b3 - v37 (5) = Lsh64x64 <int> [false] v13 v70 v22 (5) = AddPtr <*float32> v64 v37 v24 (5) = Load <float32> v22 v76 Plain → b8 (+5 ) b8 : ← b6 - v35 (5) = Mul32F <float32> v24 v24 v39 (5) = IsInBounds <bool> v13 v60 If v39 → b10 b11 (likely) (5) b10 : ← b8 - v43 (5) = AddPtr <*float32> v61 v37 v45 (5) = Load <float32> v43 v76 Plain → b12 (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b10 - v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v63 (5) = IsInBounds <bool> v13 v47 If v63 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
check bce + branchelim + late fuse
check bce [297 ns] branchelim [4355 ns] late fuse [1950 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = Const64 <int> [0] (i[int])v71 (?) = Const64 <int> [1]v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])v70 (5) = Const64 <uint64> [2]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v14 (+4 ) = Less64 <bool> v13 v68 If v14 → b8 b5 (likely) (4) b4 : ← b12 - v67 (5) = AddPtr <*float32> v40 v37 v69 (5) = Store <mem> {float32} v67 v59 v76 v72 (+4 ) = Add64 <int> v13 v71 (i[int])Plain → b2 (4) b8 : ← b2 - v37 (5) = Lsh64x64 <int> [false] v13 v70 v39 (5) = IsInBounds <bool> v13 v60 v22 (+5 ) = AddPtr <*float32> v64 v37 v24 (5) = Load <float32> v22 v76 v35 (+5 ) = Mul32F <float32> v24 v24 If v39 → b12 b11 (likely) (5) b11 : ← b8 - v41 (5) = PanicBounds <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b8 - v43 (5) = AddPtr <*float32> v61 v37 v45 (5) = Load <float32> v43 v76 v56 (5) = Mul32F <float32> v45 v45 v57 (5) = Add32F <float32> v35 v56 v59 (5) = Neg32F <float32> v57 v63 (5) = IsInBounds <bool> v13 v47 If v63 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = PanicBounds <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
dse + writebarrier + lower
dse [4356 ns] writebarrier [2956 ns] lower [208278 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])v71 (?) = MOVQconst <int> [1]v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])v70 (5) = MOVQconst <uint64> [2]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 v14 (+4 ) = SETL <bool> v30 v51 (+4 ) = TESTB <flags> v14 v14 LT v30 → b8 b5 (likely) (4) b4 : ← b12 - v67 (5) = LEAQ4 <*float32> v40 v13 v69 (5) = MOVSSstore <mem> v67 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])Plain → b2 (4) b8 : ← b2 - v22 (+5 ) = LEAQ4 <*float32> v64 v13 v24 (5) = MOVSSload <float32> v22 v76 v35 (+5 ) = MULSS <float32> v24 v24 v18 (5) = SHLQconst <int> [2] v13 v23 (5) = MOVQconst <int> [-1]v46 (5) = FlagLT_ULT <flags>v54 (5) = CMPQ <flags> v13 v60 v39 (5) = SETB <bool> v54 v20 (5) = TESTB <flags> v39 v39 ULT v54 → b12 b11 (likely) (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b8 - v43 (5) = LEAQ4 <*float32> v61 v13 v45 (5) = MOVSSload <float32> v43 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v9 (5) = MOVSSconst <float32> [-0]v8 (5) = CMPQ <flags> v13 v47 v59 (5) = PXOR <float32> v57 v9 v63 (5) = SETB <bool> v8 v50 (5) = TESTB <flags> v63 v63 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
addressing modes
addressing modes [8665 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])v71 (?) = MOVQconst <int> [1]v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])v70 (5) = MOVQconst <uint64> [2]Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 v14 (+4 ) = SETL <bool> v30 v51 (+4 ) = TESTB <flags> v14 v14 LT v30 → b8 b5 (likely) (4) b4 : ← b12 - v67 (5) = LEAQ4 <*float32> v40 v13 v69 (5) = MOVSSstoreidx4 <mem> v40 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])Plain → b2 (4) b8 : ← b2 - v22 (+5 ) = LEAQ4 <*float32> v64 v13 v24 (5) = MOVSSloadidx4 <float32> v64 v13 v76 v35 (+5 ) = MULSS <float32> v24 v24 v18 (5) = SHLQconst <int> [2] v13 v23 (5) = MOVQconst <int> [-1]v46 (5) = FlagLT_ULT <flags>v54 (5) = CMPQ <flags> v13 v60 v39 (5) = SETB <bool> v54 v20 (5) = TESTB <flags> v39 v39 ULT v54 → b12 b11 (likely) (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b8 - v43 (5) = LEAQ4 <*float32> v61 v13 v45 (5) = MOVSSloadidx4 <float32> v61 v13 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v9 (5) = MOVSSconst <float32> [-0]v8 (5) = CMPQ <flags> v13 v47 v59 (5) = PXOR <float32> v57 v9 v63 (5) = SETB <bool> v8 v50 (5) = TESTB <flags> v63 v63 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
lowered deadcode for cse
lowered deadcode for cse [10377 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 LT v30 → b8 b5 (likely) (4) b4 : ← b12 - v69 (5) = MOVSSstoreidx4 <mem> v40 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])Plain → b2 (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v64 v13 v76 v35 (+5 ) = MULSS <float32> v24 v24 v54 (5) = CMPQ <flags> v13 v60 ULT v54 → b12 b11 (likely) (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v61 v13 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v9 (5) = MOVSSconst <float32> [-0]v8 (5) = CMPQ <flags> v13 v47 v59 (5) = PXOR <float32> v57 v9 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
lowered cse + elim unread autos + tighten tuple selectors + lowered deadcode + checkLower + late phielim + late copyelim + tighten
lowered cse [16997 ns] elim unread autos [1468 ns] tighten tuple selectors [706 ns] lowered deadcode [5479 ns] checkLower [608 ns] late phielim [945 ns] late copyelim [1279 ns] tighten [21899 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 LT v30 → b8 b5 (likely) (4) b4 : ← b12 - v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])v9 (5) = MOVSSconst <float32> [-0]v59 (5) = PXOR <float32> v57 v9 v69 (5) = MOVSSstoreidx4 <mem> v40 v13 v59 v76 Plain → b2 (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v64 v13 v76 v35 (+5 ) = MULSS <float32> v24 v24 v54 (5) = CMPQ <flags> v13 v60 ULT v54 → b12 b11 (likely) (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v61 v13 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v8 (5) = CMPQ <flags> v13 v47 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
late deadcode + critical + phi tighten + likelyadjust + layout
late deadcode [5479 ns] critical [1399 ns] phi tighten [687 ns] likelyadjust [1222 ns] layout [4291 ns] b1 :- v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v61 (3 ) = Arg <*float32> {b} (b[*float32])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v47 (3 ) = Arg <int> {c} [8] (c+8[int])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 LT v30 → b8 b5 (likely) (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v64 v13 v76 v35 (+5 ) = MULSS <float32> v24 v24 v54 (5) = CMPQ <flags> v13 v60 ULT v54 → b12 b11 (likely) (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v61 v13 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v8 (5) = CMPQ <flags> v13 v47 ULT v8 → b4 b15 (likely) (5) b4 : ← b12 - v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])v9 (5) = MOVSSconst <float32> [-0]v59 (5) = PXOR <float32> v57 v9 v69 (5) = MOVSSstoreidx4 <mem> v40 v13 v59 v76 Plain → b2 (4) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
schedule
schedule [55631 ns] b1 :- v47 (3 ) = Arg <int> {c} [8] (c+8[int])v60 (3 ) = Arg <int> {b} [8] (b+8[int])v40 (3 ) = Arg <*float32> {c} (c[*float32])v61 (3 ) = Arg <*float32> {b} (b[*float32])v64 (3 ) = Arg <*float32> {a} (a[*float32])v68 (3 ) = Arg <int> {a} [8] (a+8[int])v1 (?) = InitMem <mem>v10 (?) = MOVQconst <int> [0] (i[int])Plain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v10 v72 (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v68 LT v30 → b8 b5 (likely) (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v64 v13 v76 v35 (+5 ) = MULSS <float32> v24 v24 v54 (5) = CMPQ <flags> v13 v60 ULT v54 → b12 b11 (likely) (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v61 v13 v76 v56 (5) = MULSS <float32> v45 v45 v57 (5) = ADDSS <float32> v35 v56 v8 (5) = CMPQ <flags> v13 v47 ULT v8 → b4 b15 (likely) (5) b4 : ← b12 - v9 (5) = MOVSSconst <float32> [-0]v59 (5) = PXOR <float32> v57 v9 v69 (5) = MOVSSstoreidx4 <mem> v40 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 (i[int])Plain → b2 (4) b15 : ← b12 - v65 (5) = LoweredPanicBoundsC <mem> [0] v13 v47 v76 Exit v65 (5) b11 : ← b8 - v41 (5) = LoweredPanicBoundsC <mem> [0] v13 v60 v76 Exit v41 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
late nilcheck + flagalloc + regalloc
late nilcheck [3713 ns] flagalloc [6660 ns] regalloc [371617 ns] b1 :- v47 (3 ) = Arg <int> {c} [8] : c+8[int] (c+8[int])v60 (3 ) = Arg <int> {b} [8] : b+8[int] (b+8[int])v40 (3 ) = Arg <*float32> {c} : c[*float32] (c[*float32])v61 (3 ) = Arg <*float32> {b} : b[*float32] (b[*float32])v64 (3 ) = Arg <*float32> {a} : a[*float32] (a[*float32])v68 (3 ) = Arg <int> {a} [8] : a+8[int] (a+8[int])v1 (?) = InitMem <mem>v50 (4 ) = LoadReg <int> v68 : DXv63 (4 ) = LoadReg <*float32> v40 : BXv43 (4 ) = LoadReg <int> v47 : SIv46 (4 ) = LoadReg <int> v60 : DIv23 (4 ) = LoadReg <*float32> v61 : R8v18 (4 ) = LoadReg <*float32> v64 : R9v67 (?) = MOVQconst <int> [0] : AXPlain → b2 (+4 ) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v67 v72 : AX (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v50 LT v30 → b8 b5 (likely) (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v18 v13 v76 : X0v35 (+5 ) = MULSS <float32> v24 v24 : X0v54 (5) = CMPQ <flags> v13 v46 ULT v54 → b12 b11 (likely) (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v23 v13 v76 : X1v56 (5) = MULSS <float32> v45 v45 : X1v57 (5) = ADDSS <float32> v35 v56 : X0v8 (5) = CMPQ <flags> v13 v43 ULT v8 → b4 b15 (likely) (5) b4 : ← b12 - v20 (5 ) = MOVSSconst <float32> [-0] : X1v59 (5) = PXOR <float32> v57 v20 : X0v69 (5) = MOVSSstoreidx4 <mem> v63 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 : AX (i[int])Plain → b2 (4) b15 : ← b12 - v22 (5 ) = Copy <int> v43 : CXv65 (5) = LoweredPanicBoundsC <mem> [0] v13 v22 v76 Exit v65 (5) b11 : ← b8 - v39 (5 ) = Copy <int> v46 : CXv41 (5) = LoweredPanicBoundsC <mem> [0] v13 v39 v76 Exit v41 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
loop rotate
loop rotate [3955 ns] b1 :- v47 (3 ) = Arg <int> {c} [8] : c+8[int] (c+8[int])v60 (3 ) = Arg <int> {b} [8] : b+8[int] (b+8[int])v40 (3 ) = Arg <*float32> {c} : c[*float32] (c[*float32])v61 (3 ) = Arg <*float32> {b} : b[*float32] (b[*float32])v64 (3 ) = Arg <*float32> {a} : a[*float32] (a[*float32])v68 (3 ) = Arg <int> {a} [8] : a+8[int] (a+8[int])v1 (?) = InitMem <mem>v50 (4 ) = LoadReg <int> v68 : DXv63 (4 ) = LoadReg <*float32> v40 : BXv43 (4 ) = LoadReg <int> v47 : SIv46 (4 ) = LoadReg <int> v60 : DIv23 (4 ) = LoadReg <*float32> v61 : R8v18 (4 ) = LoadReg <*float32> v64 : R9v67 (?) = MOVQconst <int> [0] : AXPlain → b2 (+4 ) b4 : ← b12 - v20 (5 ) = MOVSSconst <float32> [-0] : X1v59 (5) = PXOR <float32> v57 v20 : X0v69 (5) = MOVSSstoreidx4 <mem> v63 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 : AX (i[int])Plain → b2 (4) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v67 v72 : AX (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v50 LT v30 → b8 b5 (likely) (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v18 v13 v76 : X0v35 (+5 ) = MULSS <float32> v24 v24 : X0v54 (5) = CMPQ <flags> v13 v46 ULT v54 → b12 b11 (likely) (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v23 v13 v76 : X1v56 (5) = MULSS <float32> v45 v45 : X1v57 (5) = ADDSS <float32> v35 v56 : X0v8 (5) = CMPQ <flags> v13 v43 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v22 (5 ) = Copy <int> v43 : CXv65 (5) = LoweredPanicBoundsC <mem> [0] v13 v22 v76 Exit v65 (5) b11 : ← b8 - v39 (5 ) = Copy <int> v46 : CXv41 (5) = LoweredPanicBoundsC <mem> [0] v13 v39 v76 Exit v41 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
stackframe + trim
stackframe [4945 ns] trim [856 ns] b1 :- v47 (3 ) = Arg <int> {c} [8] : c+8[int] (c+8[int])v60 (3 ) = Arg <int> {b} [8] : b+8[int] (b+8[int])v40 (3 ) = Arg <*float32> {c} : c[*float32] (c[*float32])v61 (3 ) = Arg <*float32> {b} : b[*float32] (b[*float32])v64 (3 ) = Arg <*float32> {a} : a[*float32] (a[*float32])v68 (3 ) = Arg <int> {a} [8] : a+8[int] (a+8[int])v1 (?) = InitMem <mem>v50 (4 ) = LoadReg <int> v68 : DXv63 (4 ) = LoadReg <*float32> v40 : BXv43 (4 ) = LoadReg <int> v47 : SIv46 (4 ) = LoadReg <int> v60 : DIv23 (4 ) = LoadReg <*float32> v61 : R8v18 (4 ) = LoadReg <*float32> v64 : R9v67 (?) = MOVQconst <int> [0] : AXPlain → b2 (+4 ) b4 : ← b12 - v20 (5 ) = MOVSSconst <float32> [-0] : X1v59 (5) = PXOR <float32> v57 v20 : X0v69 (5) = MOVSSstoreidx4 <mem> v63 v13 v59 v76 v72 (+4 ) = ADDQconst <int> [1] v13 : AX (i[int])Plain → b2 (4) b2 : ← b1 b4 - v13 (4 ) = Phi <int> v67 v72 : AX (i[int])v76 (5 ) = Phi <mem> v1 v69 v30 (+4 ) = CMPQ <flags> v13 v50 LT v30 → b8 b5 (likely) (4) b8 : ← b2 - v24 (+5 ) = MOVSSloadidx4 <float32> v18 v13 v76 : X0v35 (+5 ) = MULSS <float32> v24 v24 : X0v54 (5) = CMPQ <flags> v13 v46 ULT v54 → b12 b11 (likely) (5) b12 : ← b8 - v45 (5) = MOVSSloadidx4 <float32> v23 v13 v76 : X1v56 (5) = MULSS <float32> v45 v45 : X1v57 (5) = ADDSS <float32> v35 v56 : X0v8 (5) = CMPQ <flags> v13 v43 ULT v8 → b4 b15 (likely) (5) b15 : ← b12 - v22 (5 ) = Copy <int> v43 : CXv65 (5) = LoweredPanicBoundsC <mem> [0] v13 v22 v76 Exit v65 (5) b11 : ← b8 - v39 (5 ) = Copy <int> v46 : CXv41 (5) = LoweredPanicBoundsC <mem> [0] v13 v39 v76 Exit v41 (5) name a[*float32]: v64 name a+8[int]: v68 name b[*float32]: v61 name b+8[int]: v60 name c[*float32]: v40 name c+8[int]: v47 name i[int]: v10 v13 v72
genssa
genssa # /app/public/buildbox/8a28c38c-73b9-4cfc-b785-d9b7213ecd6b/main.go 00000 (3) TEXT "".scalarComputation(SB), ABIInternal 00001 (3) FUNCDATA $0, gclocals·1ad11ff70e734d54d0be78984ccb81ed(SB) 00002 (3) FUNCDATA $1, gclocals·69c1753bd5f81501d95132d08af04464(SB) v50 00003 (+4 ) MOVQ "".a+8(SP), DX v63 00004 (4 ) MOVQ "".c+48(SP), BX v43 00005 (4 ) MOVQ "".c+56(SP), SI v46 00006 (4 ) MOVQ "".b+32(SP), DI v23 00007 (4 ) MOVQ "".b+24(SP), R8 v18 00008 (4 ) MOVQ "".a(SP), R9 v67 00009 (4 ) XORL AX, AX b1 00010 (4 ) JMP 15 v20 00011 (5 ) MOVSS $(-0.0), X1 v59 00012 (5 ) PXOR X1, X0 v69 00013 (5 ) MOVSS X0, (BX)(AX*4) v72 00014 (+4 ) INCQ AX v30 00015 (+4 ) CMPQ AX, DX b2 00016 (4 ) JGE 27 v24 00017 (+5 ) MOVSS (R9)(AX*4), X0 v35 00018 (5 ) MULSS X0, X0 v54 00019 (5 ) CMPQ AX, DI b8 00020 (5 ) JCC 31 v45 00021 (5 ) MOVSS (R8)(AX*4), X1 v56 00022 (5 ) MULSS X1, X1 v57 00023 (5 ) ADDSS X1, X0 v8 00024 (5 ) CMPQ AX, SI b12 00025 (5 ) JCS 11 b12 00026 (5 ) JMP 28 b5 00027 (4) RET v22 00028 (5 ) MOVQ SI, CX v65 00029 (5 ) PCDATA $1, $1 v65 00030 (5 ) CALL runtime.panicIndex(SB) v39 00031 (5 ) MOVQ DI, CX v41 00032 (5 ) CALL runtime.panicIndex(SB) 00033 (5) XCHGL AX, AX 00034 (?) END